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HT49RV5/HT49CV5 A/D With VFD Type 8-Bit MCU
Technical Document
* Tools Information * FAQs * Application Note - HA0077E HT49CVX Remote Control Receiver SWIP Design Note - HA0078E HT49CVX Display SWIP Design Note
Features
* Operating voltage: * 8-bit prescaler for RTC * Watchdog Timer * Buzzer output * On-chip crystal, RC and 32768Hz crystal oscillator * HALT function and wake-up feature reduce power
fSYS=4MHz: 2.2V~5.5V fSYS=8MHz: 3.3V~5.5V
* 20 bidirectional I/O lines (PA, PB, PC, PD) * Two external interrupt inputs * Two 16-bit programmable timer/event counters with
consumption
* 8-level subroutine nesting * 4-channel 8-bit resolution A/D converter * 2-channel 8-bit PWM output shared with 2 I/O lines * Low voltage reset function * Bit manipulation instruction * 16-bit table read instruction * Up to 0.5ms instruction cycle with 8MHz system clock * 63 powerful instructions * All instructions in 1 or 2 machine cycles * 56-pin SSOP package
PFD (programmable frequency divider) function
* One 8-bit Remote Control Timer (RMT), pin-shared
with PC7
* Single channel serial interface * VFD driver with 1111 segments
(16-segment & 4-grid to 11-segment & 11-grid)
* 4K16 program memory * 1928 data memory RAM * Supports PFD for sound generation * Real Time Clock (RTC)
General Description
The HT49RV5/HT49CV5 are 8-bit high performance single chip MCUs. Their single cycle instruction and 2-stage pipeline architecture make them suitable for high speed applications. As the devices include an VFD driver they are suitable for use in products which require a front panel for their operation such as DVDs, VCDs, Mini-component audio systems, cassette decks, tuners, CD players, other home appliances, etc.
Rev. 1.20
1
April 14, 2006
HT49RV5/HT49CV5
Block Diagram
In te rru p t C ir c u it P ro g ra m ROM P ro g ra m C o u n te r S ta c k IN T C
TM R0C TM R0 PFD0 TM R1C TM R1 PFD1 M
M U
P r e s c a le r X P D 6 /T M R 0 P D 7 /T M R 1 U X fS
YS
fS
YS
/4
32768Hz M U X fS M U X
YS
In s tr u c tio n R e g is te r
RTC MP M U X D a ta M e m o ry W DT
/4 OSC
RTC
OSC3 OSC4
In s tr u c tio n D ecoder ALU T im in g G e n e r a tio n
MUX
W DT OSC PW M PDC STATUS PD 4 -C h a n n e l A /D C o n v e rte r BP PBC PB VFD M e m o ry PAC PA H ALT LVR PCC PC E N /D IS PORT B P B 0 /A N 0 ~ P B 3 /A N 3 PA0 PA1 PA2 PA3 PA4 /B Z /B Z /P F D ~PA7 PORT D PD PD PD PD PD 0/ 4/ 5/ 6/ 7/ PW IN IN TM TM M 0 ~ P D 1 /P W T0 T1 R0 R1 M1
S h ifte r
OSC2 OSC4
OS OS VD VS RE S
D S
C1 C3
ACC
PORT A
VEE
V F D D r iv e r
G r id 0 ~ G r id 5
S E G 1 1 /G r id 1 0 ~ S E G 1 5 /G r id 6
SEG 0~ SEG 10
PORT C
PC6 P C 7 /R M T SDI SDO SCK SCS
S e r ia l In te r fa c e
MUX fS fR 8 - b it R e m o te C o n tr o l T im e r
Y S /4 TCOSC
RMT
Rev. 1.20
2
April 14, 2006
HT49RV5/HT49CV5
Pin Assignment
OSC2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 OSC1 RES P A 0 /B Z P A 1 /B Z PA2 P A 3 /P F D PA4 PA5 PA6 PA7 P B 0 /A N 0 P B 1 /A N 1 P B 2 /A N 2 P B 3 /A N 3 VSS P D 0 /P W M 0 P D 1 /P W M 1 P D 4 /IN T 0 P D 5 /IN T 1 P D 6 /T M R 0 P D 7 /T M R 1 VSS PC6 P C 7 /R M T SEG0 SEG1 SEG2 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDD OSC3 OSC4 SDI SDO SCK SCS G R ID 0 G R ID 1 G R ID 2 G R ID 3 G R ID 4 G R ID 5 VDD VEE S E G 1 5 /G R ID 6 S E G 1 4 /G R ID 7 S E G 1 3 /G R ID 8 S E G 1 2 /G R ID 9 S E G 1 1 /G R ID 1 0 SEG 10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3
H T 4 9 R V 5 /H T 4 9 C V 5 5 6 S S O P -A
Note:
Each VDD (VSS) pins must be connected to the power (ground) of the system.
Pin Description
Pin Name PA0/BZ PA1/BZ PA2 PA3/PFD PA4~PA7 I/O Options Wake-up Pull-high Buzzer PFD Description Bidirectional 8-bit input/output port. Each bit can be configured as a wake-up input by configuration option. Software instructions determine if the pin is a CMOS output or Schmitt trigger input with or without pull-high resistor (determined by pull-high options: bit option). Pins PA0, PA1 and PA3 are pin-shared with BZ, BZ and PFD, respectively. Bidirectional 4-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt trigger input with or without pull-high resistor (determined by pull-high option: bit option) or A/D input. Once a PB line is selected as an A/D input (by using software control), the I/O function and pull-high resistor are disabled automatically. Bidirectional 2-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt trigger input with or without pull-high resistor (determined by pull-high option: bit option). RMT with wake-up function (both rising and falling edge) and Schmitt trigger input with or without a pull-high resistor (determined by pull-high option). Note:The RMT is pin-shared with PC7. When PC7/RMT pin uses as the input mode of RMT function , suggesting the user to set PC7 as input mode for safety. And so that I/O function of PC7 will not influence the RMT input function.
I/O
PB0/AN0~ PB3/AN3
I/O
Pull-high
PC6 PC7/RMT
I/O
Pull-high
Rev. 1.20
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April 14, 2006
HT49RV5/HT49CV5
Pin Name PD0/PWM0 PD1/PWM1 I/O Options Pull-high PWM Description Bidirectional 2-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt trigger input with or without a pull-high resistor (determined by pull-high option: bit option). PD0~PD1 are pin-shared with PWM0~PWM1 (dependent on Mask options). Bidirectional 4-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt trigger input with or without a pull-high resistor (determined by pull-high option: bit option). Pins PD4~PD7 are pin-shared with INT0, INT1, TMR0 & TMR1, respectively (determined by software control). Negative power supply, ground VFD Negative power supply High voltage segment output for VFD panel. High voltage output for VFD panel. These pins are selectable for segment or grid output. High voltage grid output for VFD panel. Serial interface serial data input Serial interface serial data output Serial interface serial clock input/output (initial input). Serial interface chip select pin, output for master mode, input for slave mode.
I/O
PD4/INT0 PD5/INT1 PD6/TMR0 PD7/TMR1 VSS VEE SEG0~SEG10 SEG11/Grid10~ SEG15/Grid6 Grid0~Grid5 SDI SDO SCK SCS OSC4 OSC3 VDD OSC2 OSC1 RES
I/O
Pull-high
3/4 3/4 O O O I O I/O I/O O I 3/4 O I I
3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
Real time clock oscillators. OSC3 and OSC4 are connected to a 32768Hz RTC or crystal oscillator for timing purposes or to a system clock source (depending System Clock on the options). No built-in capacitor. 3/4 Crystal or RC 3/4 Positive power supply OSC1 and OSC2 are connected to an RC network or a crystal (by options) for the internal system clock. For RC operation, OSC2 is an output pin for 1/4 system clock. The system clock may come from the RTC oscillator. If the system clock comes from RTCOSC, these two pins can be left floating. Schmitt trigger reset input, active low
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V Input Voltage..............................VSS-0.3V to VDD+0.3V Storage Temperature ............................-50C to 125C Operating Temperature...........................-40C to 85C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.20
4
April 14, 2006
HT49RV5/HT49CV5
D.C. Characteristics
Symbol Parameter Test Conditions VDD 3/4 3/4 3/4 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 5V 5V 3V 5V 5V 3/4 3/4 3V 5V 3V 5V No load VOL=0.1VDD Conditions fSYS=4MHz fSYS=8MHz 3/4 No load, ADC off, VFD off, fSYS=4MHz No load, ADC off, VFD off, fSYS=4MHz No load, ADC off, VFD off No load, ADC off, VFD on, fSYS=4MHz No load, system HALT VFD off at HALT No load, system HALT VFD off at HALT 3/4 3/4 3/4 3/4 Min. 2.2 3.3 0 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 0 0.8VDD 0 0.9VDD 6 10 -2 -5 -15 -3 20 10 50 2.7 0 3/4 3/4 3/4 Typ. 3/4 3/4 3/4 2.0 5.0 1.8 4.6 1.2 4 3.5 7.5 3/4 3/4 4 14 3/4 3/4 3/4 3/4 12 25 -4 -8 3/4 3/4 60 30 100 3.0 3/4 0.5 1 2 Max. 5.5 5.5 VDD-30 3.0 8.0 2.7 7.5 2 7 4.5 12 1 2 10 20 0.2VDD VDD 0.4VDD VDD 3/4 3/4 3/4 3/4 3/4 3/4 100 50 150 3.3 VDD 1 2 4 Ta=25C Unit V V V mA mA mA mA mA mA mA mA mA mA mA mA V
VDD VEE IDD1
Operating Voltage VFD Supply Voltage Operating Current (Crystal OSC)
IDD2
Operating Current (RC OSC) Operating Current (fSYS=32768Hz) Operating Current (Crystal OSC)
IDD3
IDD4
ISTB1
Standby Current (*fS=T1) Standby Current (*fS=32768Hz OSC) Input Low Voltage for I/O Ports, TMR and INT Input High Voltage for I/O Ports, TMR and INT Input Low Voltage (RES)
ISTB2 VIL1 VIH1 VIL2 VIH2 IOL
V
V
Input High Voltage (RES)
V mA mA mA mA mA mA kW kW kW V V LSB mA mA
I/O Port Sink Current
IOH1 IOH2 IOH3 RPH RPL VLVR VAD EAD IADC Note:
I/O Port Source Current Grid Source Current Segment Source Current Pull-high Resistance of I/O Ports and INT0, INT1 VFD Driver Output Pull-low Resistor Low Voltage Reset Voltage A/D Input Voltage A/D Conversion Error Additional Power Consumption if A/D Converter is Used *fS Refer to WDT clock option
VOH=0.9VDD VOH=VDD-2V VOH=VDD-2V 3/4 3/4 3/4 LVR enabled 3/4 3/4
Rev. 1.20
5
April 14, 2006
HT49RV5/HT49CV5
A.C. Characteristics
Test Conditions Symbol Parameter VDD fSYS1 System Clock System Clock (32768Hz Crystal OSC) RTC Frequency Timer I/P Frequency (TMR0/TMR1) 3/4 3/4 3/4 3/4 3/4 3/4 3V 5V tRES tSST tINT tAD tADC tADCS Note: External Reset Low Pulse Width System Start-up Timer Period Interrupt Pulse Width A/D Clock Period A/D Conversion Time A/D Sampling Time tSYS= 1/fSYS 3/4 3/4 3/4 3/4 3/4 3/4 2.2V~5.5V 3.3V~5.5V 3/4 3/4 3/4 Power-up or wake-up from HALT 3/4 3/4 3/4 3/4 Conditions 2.2V~5.5V 3.3V~5.5V 2.2V~5.5V 3/4 400 400 3/4 3/4 0 0 45 32 1 3/4 1 1 3/4 3/4 3/4 3/4 32768 32768 3/4 3/4 90 65 3/4 1024 3/4 3/4 76 32 4000 8000 3/4 3/4 4000 8000 180 130 3/4 3/4 3/4 3/4 3/4 3/4 kHz kHz Hz Hz kHz kHz ms ms ms tSYS ms ms tAD tAD Min. Typ. Max. Unit Ta=25C
fSYS2 fRTCOSC fTIMER
tWDTOSC Watchdog Oscillator Period
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April 14, 2006
HT49RV5/HT49CV5
Functional Description
Execution Flow The system clock is derived from either a crystal or an RC oscillator or a 32768Hz crystal oscillator. It is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle. The pipelining scheme ensures that instructions are effectively executed in one cycle. Exceptions to this are instructions that change the contents of the program counter, such as subroutine calls or jumps, in which case, two cycles are required to complete the instruction. Program Counter - PC The 12-bit program counter (PC) controls the sequence in which the instructions stored in the program ROM are
S y s te m O S C 2 (R C C lo c k o n ly ) PC PC PC+1 PC+2 T1 T2 T3 T4 T1 T2
executed and its contents specify a maximum of 4096 addresses. After accessing a program memory word to fetch an instruction code, the contents of the program counter are incremented by one. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from subroutine, etc., the microcontroller manages program control by loading the address corresponding to each instruction. For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the current instruction execution, is discarded and a dummy cycle replaces it while the proper instruction is obtained. Otherwise proceed with the next instruction.
T3 T4 T1 T2 T3 T4
F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 )
Execution Flow Program Counter Mode *11 Initial Reset External Interrupt 0 External Interrupt 1 Timer/Event Counter 0 Overflow Timer/Event Counter 1 Overflow Serial Interface Interrupt Multi-function Interrupt Skip Loading PCL Jump, Call Branch Return from Subroutine *11 #11 S11 *10 #10 S10 *9 #9 S9 *8 #8 S8 0 0 0 0 0 0 0 *10 0 0 0 0 0 0 0 *9 0 0 0 0 0 0 0 *8 0 0 0 0 0 0 0 *7 0 0 0 0 0 0 0 *6 0 0 0 0 0 0 0 *5 0 0 0 0 0 0 0 *4 0 0 0 0 1 1 1 *3 0 0 1 1 0 0 1 *2 0 1 0 1 0 1 0 *1 0 0 0 0 0 0 0 *0 0 0 0 0 0 0 0
Program Counter+2 @7 #7 S7 @6 #6 S6 @5 #5 S5 @4 #4 S4 @3 #3 S3 @2 #2 S2 @1 #1 S1 @0 #0 S0
Program Counter Note: *11~*0: Program counter bits #11~#0: Instruction code bits S11~S0: Stack register bits @7~@0: PCL bits
Rev. 1.20
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April 14, 2006
HT49RV5/HT49CV5
The lower byte of the program counter (PCL) is available for program control and is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destination will be within 256 locations. When a control transfer takes place, an additional dummy cycle is required. Program Memory - EPROM The program memory (EPROM) is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 409616 bits format. The program counter is composed of 12 bits, so it can directly access the whole program memory without changing banks. Certain locations in the ROM are reserved for special usage:
* Location 000H * Location 008H
This area is reserved for the external interrupt service program. If the INT1 input pin is activated, and the interrupt is enabled, and the stack is not full, the program will jump to this location and begin execution.
* Location 00CH
This area is reserved for the Timer/Event Counter 0 interrupt service program. If a timer interrupt results from a Timer/Event Counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program will jump to this location and begin execution.
* Location 010H
This area is reserved for the Timer/Event Counter 1 interrupt service program. If a timer interrupt results from a Timer/Event Counter 1 overflow, and if the interrupt is enabled and the stack is not full, the program will jump to this location and begin execution.
* Location 014H
This area is reserved for use by the chip reset for program initialization. After a chip reset is initiated, the program will jump to this location and begin execution.
* Location 004H
This area is reserved for the external interrupt service program. If the INT0 input pin is activated, and the interrupt is enabled, and the stack is not full, the program will jump to this location and begin execution.
000H 004H 008H 00C H 010H 014H 018H n00H nFFH D e v ic e In itia liz a tio n P r o g r a m E x te r n a l In te r r u p t 0 S u b r o u tin e E x te r n a l In te r r u p t 1 S u b r o u tin e T im e r /E v e n t C o u n te r 0 In te r r u p t S u b r o u tin e T im e r /E v e n t C o u n te r 1 In te r r u p t S u b r o u tin e S e r ia l In te r fa c e In te r r u p t M u lti- fu n c tio n In te r r u p t L o o k - u p T a b le ( 2 5 6 W o r d s )
This area is reserved for the Serial Interface interrupt service program. If 8 bits of data have been received or transmitted successfully from the serial interface, and the interrupt is enabled, and the stack is not full, the program will jump to this location and begin execution.
* Location 018H
This area is reserved for the multi-function interrupt. If a real time clock interrupt occurs, or if a rising edge is detected from the RMT input pin, or if a falling edge is detected from the RMT input pin, or if the RMT overflow and the related interrupts are enabled, and the stack is not full, the program will jump to this location and begin execution.
* Table location
P ro g ra m ROM
FFFH
L o o k - u p T a b le ( 2 5 6 W o r d s ) 1 6 b its N o te : n ra n g e s fro m 0 to F
Program Memory
Any location within the program memory can be used as a look-up table where programmers can store fixed data. The instructions TABRDC [m] (the current page, 1 page=256 words) and TABRDL [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the contents of the higher-order byte to TBLH (Table Higher-order byte register) (08H). Only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are all transferred to the lower portion of TBLH. The TBLH is a read only register and the table pointer (TBLP) is a read/write register (07H), which indicates the table location. Before accessing the table, the location must be placed in the TBLP. All table re-
Table Location Instruction(s) *11 TABRDC [m] TABRDL [m] P11 1 *10 P10 1 *9 P9 1 *8 P8 1 *7 @7 @7 *6 @6 @6 *5 @5 @5 *4 @4 @4 *3 @3 @3 *2 @2 @2 *1 @1 @1 *0 @0 @0
Table Location Note: *11~*0: Table location bits @7~@0: Table pointer bits P11~P8: Current program counter bits
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HT49RV5/HT49CV5
lated instructions require two cycles to complete the operation. These areas may function as normal program memory depending upon users requirements. Stack Register - STACK The stack register is a special part of the memory used to save the contents of the Program Counter. The stack is organized into 8 levels and is neither part of the data nor part of the program, and is neither readable nor writeable. Its activated level is indexed by a stack pointer (SP) and is neither readable nor writeable. At the start of a subroutine call or an interrupt acknowledgment, the contents of the Program Counter is pushed onto the stack. At the end of the subroutine or interrupt routine, signaled by a return instruction (RET or RETI), the contents of the Program Counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack. If the stack is full and a non-masked interrupt takes place, the interrupt request flag is recorded but the acknowledgment is still inhibited. Once the SP is decremented (by RET or RETI), the interrupt is serviced. This feature prevents stack overflow, allowing the programmer to use the structure easily. Likewise, if the stack is full, and a CALL is subsequently executed, a stack overflow occurs and the first entry is lost (only the most recent 8 return addresses are stored). Data Memory - RAM The data memory (RAM) has a capacity of 2318 bits, and is divided into two functional groups, namely; special function registers (398 bit) and general purpose data memory (RAM bank contains 1928 bits) most of which are readable/writeable, but some are read only. The special function registers are overlapped in any banks. The special function registers consist of an Indirect addressing register 0 (00H), a Memory pointer register 0 (MP0;01H), an Indirect addressing register 1 (02H), a Memory pointer register 1 (MP1;03H), a Bank pointer (BP;04H), an Accumulator (ACC;05H), a Program counter lower-order byte register (PCL;06H), a Table pointer (TBLP;07H), a Table higher-order byte register (TBLH;08H), a Real time clock control register (RTCC;09H), a Status register (STATUS;0AH), an Interrupt control register 0 (INTC0;0BH), a Timer/Event Counter 0 (TMR0H:0CH; TMR0L:0DH), a Timer/Event Counter 0 control register (TMR0C;0EH), a Timer/Event Counter 1 (TMR1H:0FH;TMR1L:10H), a Timer/Event Counter 1 control register (TMR1C; 11H), Interrupt control register 1 (INTC1;1EH), Serial Bus control register (SBCR;1FH), Serial Bus data register (SBDR; 20H), Remote timer control register (RMTC;21H), Remote control capture register 0 (RMT0;22H), Remote control
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 30H 3FH 40H ADR ADCR ACSR VFDC M F IS IN T C 1 SBCR SBDR RM TC RM T0 RM T1 In d ir e c t A d d r e s s in g R e g is te r 0 MP0 In d ir e c t A d d r e s s in g R e g is te r 1 MP1 BP ACC PCL TBLP TBLH RTCC STATUS IN T C 0 TM R0H TM R0L TM R0C TM R1H TM R1L TM R1C PA PAC PB PBC PC PCC PD PDC PW M0 PW M1 S p e c ia l P u r p o s e D a ta M e m o ry
FFH
G e n e ra l P u rp o s e D a ta M e m o ry (1 9 2 B y te s )
:U nused R e a d a s "0 0 "
RAM Mapping capture register 1 (RMT1;23H), Multi-function interrupt status register (MFIS;29H), PWM data register (PWM0;1AH, PWM1;1BH), the A/D result register (ADR;25H), the A/D control register (ADCR;26H), the A/D clock setting register (ACSR;27H), VFD control register (VFDC; 28H), I/O registers (PA;12H, PB;14H, PC;16H, PD;18H) and I/O control registers (PAC;13H, PBC;15H, PCC;17H, PDC;19H).
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HT49RV5/HT49CV5
The remaining space before 40H is reserved for future expanded usage and reading these locations will return the result 00H. The space before 40H overlaps in each bank. The general-purpose data memory, addressed from 40H to FFH (Bank0; BP=0), is used for data and control information under instruction commands. All data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and reset by SET [m].i and CLR [m].i. They are also indirectly accessible through memory pointer registers (MP0;01H/MP1;03H). Indirect Addressing Register Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation of [00H] and [02H] accesses the RAM pointed to by MP0 (01H) and MP1(03H), respectively. Reading location 00H or 02H indirectly returns the result 00H. Writing indirectly leads to no operation. The function of data movement between two indirect addressing registers is not supported. The memory pointer registers, MP0 and MP1, are both 8-bit registers used to access the RAM by combining corresponding indirect addressing registers. MP0 can only be applied to data memory, while MP1 can be applied to data memory and VFD display memory. Accumulator - ACC The accumulator (ACC) is closely related with operations carried out by the ALU. It is mapped to location 05H of the RAM and is capable of operating with immediate data. The data movement between two data memory locations must pass through the ACC. Bit No. 0 Label C Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic operations and provides the following functions:
* Arithmetic operations (ADD, ADC, SUB, SBC, DAA) * Logic operations (AND, OR, XOR, CPL) * Rotation (RL, RR, RLC, RRC) * Increment and Decrement (INC, DEC) * Branch decision (SZ, SNZ, SIZ, SDZ etc.)
The ALU not only saves the results of a data operation but also changes the status register. Status Register - STATUS The status register (0AH) is 8 bits wide and contains a carry flag (C), an auxiliary carry flag (AC), a zero flag (Z), an overflow flag (OV), a power down flag (PDF), and a watchdog time-out flag (TO). It also records the status information and controls the operation sequence. Except for the TO and PDF flags, bits in the status register can be altered by instructions similar to other registers. Data written into the status register does not alter the TO or PDF flags. Operations related to the status register, however, may yield different results from those intended. The TO and PDF flags can only be changed by a Watchdog Timer overflow, chip power-up, or clearing the Watchdog Timer and executing a HALT instruction. The Z, OV, AC, and C flags reflect the status of the latest operations. On entering an interrupt sequence or executing a subroutine call, the status register will not be automatically pushed onto the stack. If the contents of the status is important, and if the subroutine is likely to corrupt the status register, the programmer should take precautions and save it properly.
Function C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation, otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction, otherwise AC is cleared. Z is set if the result of an arithmetic or logic operation is zero, otherwise Z is cleared. OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa, otherwise OV is cleared. PDF is cleared by either a system power-up or executing the CLR WDT instruction. PDF is set by executing the HALT instruction. TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. Unused bit, read as 0 Status (0AH) Register
1 2 3 4 5 6~7
AC Z OV PDF TO 3/4
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April 14, 2006
HT49RV5/HT49CV5
Interrupts The HT49RV5/HT49CV5 provides two external interrupts, two internal timer/event counter interrupts, three remote control timer interrupts, an internal real time clock interrupt and serial interface interrupt. The interrupt control register 0 (INTC0;0BH) and interrupt control register 1 (INTC1;1EH) both contain the interrupt control bits that are used to set the enable/disable status and interrupt request flags. Once an interrupt subroutine is serviced, all other interrupts are blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may take place during this interval, but only the interrupt request flag will be recorded. If another interrupt requires servicing while the program is in the interrupt service routine, the programmer should set the EMI bit and the corresponding bit of the INTC0 or INTC1 to allow interrupt nesting. Once the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack should be prevented from becoming full. All these interrupts can support a wake-up function. As an interrupt is serviced, a control transfer occurs by pushing the contents of the Program Counter onto the stack followed by a branch to a subroutine at the specified location in the ROM. Only the contents of the Program Counter is pushed onto the stack. If the contents of the register or of the status register (STATUS) is altered by the interrupt service program which corrupts the desired control sequence, the contents should be saved in advance. External interrupts are triggered by an edge transition of INT0 or INT1 (configuration option: high to low, low to high, low to high or high to low), and the related interrupt request flag (EIF0; bit 4 of INTC0, EIF1; bit 5 of INTC0) is set as well. After the interrupt is enabled, the stack is not full, and the external interrupt is active, a subroutine call to location 04H or 08H occurs. The interrupt request flag (EIF0 or EIF1) and EMI bits are all cleared to disable other maskable interrupts. The internal Timer/Event Counter 0 interrupt is initialized by setting the Timer/Event Counter 0 interrupt request flag (T0F; bit 6 of INTC0), which is normally caused by a timer overflow. After the interrupt is enabled, and the stack is not full, and the T0F bit is set, a subroutine call to location 0CH occurs. The related interrupt request flag (T0F) is reset, and the EMI bit is cleared to disable other maskable interrupts. Timer/Event Counter 1 is operated in the same manner but its related interrupt request flag is T1F (bit 4 of INTC1) and its subroutine call location is 10H. The Serial Interface interrupt is initialized by setting the interrupt request flag (TRF; bit 5 of INTC1), which is caused by completely receiving or transferring 8 bits of data from a serial interface. After the interrupt is enabled, and the stack is not full, and the TRF bit is set, a subroutine call to location 14H occurs. The related interrupt request flag (TRF) is reset and the EMI bit is cleared to disable further maskable interrupts. The multi-function interrupt is initialized by setting the interrupt request flag (MFF; bit 6 of INTC1), which is caused by a regular real time clock signal, or caused by a rising edge of RMT, or caused by a falling edge of RMT, or caused by an RMT overflow. After the interrupt is enabled, and the stack is not full, and the MFF bit is set, a subroutine call to location 18H occurs. The related interrupt request flag (MFF) is reset and the EMI bit is cleared to disable further maskable interrupts. During the execution of an interrupt subroutine, other maskable interrupt acknowledgments are all held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are both set to 1 (if the stack is not full). To return from the interrupt subroutine, RET or RETI may be invoked. RETI sets the EMI bit and enables an interrupt service, but RET does not. Interrupts occurring in the interval between the rising edges of two consecutive T2 pulses are serviced on the latter of the two T2 pulses if the corresponding interrupts are enabled. In the case of simultaneous requests, the following table shows the priority that is applied. These can be masked by resetting the EMI bit. Interrupt Source External interrupt 0 External interrupt 1 Timer/Event Counter 0 overflow Timer/Event Counter 1 overflow Serial Interface interrupt Multi-function interrupt Priority 1 2 3 4 5 6 Vector 04H 08H 0CH 10H 14H 18H
The RMT overflow interrupt flag (RMTVF; bit 0 of MFIS), real time clock interrupt flag (RTF; bit 1 of MFIS), the RMT rising edge interrupt flag (RMT0F; bit 2 of MFIS) and the RMT falling edge interrupt flag (RMT1F; bit 3 of MFIS) indicate that a related interrupt has occurred. After reading these flags, these flags will not be cleared automatically, they should be cleared by the user. The serial interface interrupt is indicated by the interrupt flag (TRF; bit 5 of INTC1), that is caused by receiving or transferring a complete 8-bit data transfer between the HT49RV5/ HT49CV5 and an external device. After the interrupt is enabled (by setting ESBI; bit 1 of INTC1), and the stack is not full, a subroutine call to location 14H occurs. TRF is set by SIO and should be cleared by users. The Timer/Event Counter 0 interrupt request flag (T0F), external interrupt 1 request flag (EIF1), external interrupt 0 request flag (EIF0), enable Timer/Event Counter0 11 April 14, 2006
Rev. 1.20
HT49RV5/HT49CV5
Bit No. 0 1 2 3 4 5 6 7 Label EMI EEI0 EEI1 ET0I EIF0 EIF1 T0F 3/4 Function Control the master (global) interrupt (1=enabled; 0=disabled) Control the external interrupt 0 (1=enabled; 0=disabled) Control the external interrupt 1 (1=enabled; 0=disabled) Control the Timer/Event Counter 0 interrupt (1=enabled; 0=disabled) External interrupt 0 request flag (1=active; 0=inactive) External interrupt 1 request flag (1=active; 0=inactive) Internal Timer/Event Counter 0 request flag (1=active; 0=inactive) For test mode used only. Must be written as 0; otherwise may result in unpredictable operation. INTC0 (0BH) Register Bit No. 0 1 2 3, 7 4 5 6 Label ET1I ESBI EMFI 3/4 T1F TRF MFF Function Control the Timer/Event Counter 1 interrupt (1=enabled; 0=disabled) Control the serial interface interrupt (1=enabled; 0=disabled) Control the real multi-function interrupt (1=enabled; 0=disabled) Unused bit, read as 0 Internal Timer/Event Counter 1 request flag (1=active; 0=inactive) Serial bus data transferred or data received interrupt request flag (1=active; 0=inactive) Multi-function interrupt request flag (1=active; 0=inactive) INTC1 (1EH) Register Bit No. 0 1 2 3 4 5 Label 3/4 ERMT0 ERMT1 ERMTV RME RMCS Unused bit, read as 0 Controls the remote control timer rising edge interrupt (1=enable; 0=disable) Controls the remote control timer falling edge interrupt (1=enable; 0=disable) Controls the remote control timer overflow interrupt (1=enable; 0=disable) Controls the remote control timer (1=enable; 0=disable) 1=enable & start counting; 0= disable & clear counter to 0 Selects the remote control timer clock source fX (1=fSYS; 0=fSYS/4) Selects the remote control timer clock 00=fX/25 01= fX/26 10= fX/27 11= fX/28 RMTC (21H) Register Bit No. 0 1 2 3 4 5~7 Label RMTVF RTF RMT0F RMT1F ERTI 3/4 Function Remote control timer overflow interrupt flag (1=indicates that an overflow has occurred; 0=indicates that an overflow has not occurred) Real time clock interrupt flag (1=indicates that an RTC interrupt has occurred; 0=indicates that an RTC interrupt has not occurred) Remote control timer rising edge interrupt flag (1=indicates that a rising edge interrupt has occurred; 0=indicates that a rising edge interrupt has not occurred) Remote control timer falling edge interrupt flag (1=indicates that a falling edge interrupt has occurred; 0=indicates that a falling edge interrupt has not occurred) Controls the real time clock interrupt (1=enable; 0=disable) Unused bit, read as 0 MFIS (29H) Register Rev. 1.20 12 April 14, 2006 Function
6 7
RMS0 RMS1
HT49RV5/HT49CV5
interrupt bit (ET0I), enable external interrupt 1 bit (EEI1), enable external interrupt 0 bit (EEI0), and enable master interrupt bit (EMI) constitute the Interrupt Control register 0 (INTC0) which is located at 0BH in the RAM. The multi-function interrupt request flag (MFF), serial interface interrupt request flag (TRF), Timer/Event Counter 1 interrupt request flag (T1F), enable multi-function interrupt (EMFI), enable serial interface interrupt bit (ESBI), and enable Timer/Event Counter 1 interrupt bit (ET1I), constitute the Interrupt Control register 1 (INTC1) which is located at 1EH in the RAM. The enable Remote control timer rising edge interrupt (ERMT0), enable Remote control timer falling edge interrupt (ERMT1), enable Remote control timer overflow interrupt (ERMTV), enable Remote control timer start counting (RME), select the Remote control timer clock source (RMCS), and select the Remote control timer clock (RMS0, RMS1) constitute the Remote Timer control Register (RMTC) which is located at 21H in the RAM. E M I , EE I 0, E E I 1, E T0I , E T1I , S B E N , E RT I , EMFI,ERMT0 and ERMT1 are all used to control the enable/disable status of interrupts. These bits prevent the requested interrupt from being serviced. Once the interrupt request flags (MFF, TRF, T0F, T1F, EIF1, EIF0) are all set, they remain in the INTC0~INTC1 respectively until the interrupts are serviced or cleared by a software instruction. It is recommended that a program should not use the CALL subroutine within the interrupt subroutine. This is because interrupts often occur in an unpredictable manner or require to be serviced immediately in some applications. During that period, if only one stack is left, and enabling the interrupt is not well controlled, operation of the CALL in the interrupt subroutine may damage the original control sequence. Oscillator Configuration The HT49RV5/HT49CV5 provides three oscillator circuits for system clocks, i.e., RC oscillator, crystal oscillator and 32768Hz crystal oscillator, determined by options. No matter what type of oscillator is selected, the signal is used for the system clock. The HALT mode stops the system oscillator (RC and crystal oscillator only) and ignores external signals so as to conserve power. The 32768Hz crystal oscillator still runs in the HALT mode. If the 32768Hz crystal oscillator is selected as the system oscillator, the system oscillator is not stopped but the instruction execution is stopped. Since the 32768Hz oscillator is also designed for timing purposes, the internal timing (RTC, WDT) operation still runs even if the system enters the HALT mode. Of the three oscillators, if the RC oscillator is used, an external resistor between OSC1 and VSS is required, and the range of the resistance should be from 56kW to 1.5MW. The system clock, divided by 4, is available on OSC2 with pull-high resistor, which can be used to synchronize external logic. The RC oscillator provides the most cost effective solution. However, the frequency of the oscillation may vary with VDD, temperature, and the chip itself due to process variations. It is therefore not suitable for timing sensitive operations where accurate oscillator frequency is desired. On the other hand, if the crystal oscillator is selected, a crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift for the oscillator, and no other external components are required. A resonator may be connected between OSC1 and OSC2 to replace the crystal and to get a frequency reference, but two external capacitors on OSC1 and OSC2 are required. There is another oscillator circuit designed for the real time clock. In this case, only a 32768Hz crystal oscillator can be applied. The crystal should be connected between OSC3 and OSC4. The RTC oscillator circuit can be controlled to start-up quickly by setting the QOSC bit (bit 4 of RTCC). It is recommended to turn on the quick start-up function during power-on, and then turn it off after 2 seconds. The WDT oscillator is a free running on-chip RC oscillator and no external components are required. Although the system enters the power down mode, the system clock stops and the WDT oscillator still works with a period of approximately 65ms at 5V. The WDT oscillator can be disabled by options so as to conserve power.
OSC3 OSC4 3 2 7 6 8 H z C r y s ta l/R T C O s c illa to r
OSC1 OSC2 C r y s ta l O s c illa to r
System Oscillator
OSC1 fS
YS
/4
OSC2 RC O s c illa to r
Note:
32768Hz crystal enable condition: For WDT clock source or for system clock source. The external resistor and capacitor components connected to the 32768Hz crystal are not necessary to provide oscillation. For applications where precise RTC frequencies are essential, these components may be required to provide frequency compensation due to different crystal manufacturing tolerances.
Rev. 1.20
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April 14, 2006
HT49RV5/HT49CV5
Watchdog Timer - WDT The WDT clock source is implemented by a dedicated RC oscillator (WDT oscillator) or an instruction clock (system clock/4) or a real time clock oscillator (RTC oscillator). The timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. The WDT can be disabled by options. But if the WDT is disabled, all executions related to the WDT lead to no operation. Once an internal WDT oscillator (RC oscillator with a period of 65ms at 5V) is selected, it is divided by 212~215 (by configuration option to get the WDT time-out period). The minimum WDT time-out period is 300ms~600ms. This time-out period may vary with temperature, VDD and process variations. By selecting the WDT configuration option, longer time-out periods can be realized. If the WDT time-out is selected, 215, the maximum time-out period is divided by 215~216 which is 2.3s~4.7s. If the WDT oscillator is disabled, the WDT clock may still come from the instruction clock and operates in the same manner except that in the halt state the WDT may stop counting and lose its protecting purposes. In this situation the logic can only be restarted by external logic. If the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) is strongly recommended since the HALT will stop the system clock. The WDT overflow under normal operation initializes a chip reset and sets the status bit TO. In the HALT mode, the overflow initializes a warm reset, and only the Program Counter and SP are reset to zero. To clear the contents of the WDT, there are three methods to be adopted, i.e., external reset (a low level to RES), software instruction, and a HALT instruction. There are two types of software instructions; CLR WDT and the other set - CLR WDT1 and CLR WDT2. Of these two types of instruction, only one type of instruction can be active at a time depending on the options - CLR WDT times selection option. If the CLR WDT is selected (i.e., CLR WDT times is equal to one), any execution of the CLR WDT instruction clears the WDT. In the case where the two CLR WDT1 and CLR WDT2 instructions are chosen (i.e., CLR WDT times is equal to two), these two instructions have to be executed to clear the WDT, otherwise, the WDT may reset the chip due to time-out.
S y s te m C lo c k /4
Multi-function Timer The HT49RV5/HT49CV5 provides a multi-function timer for the and RTC but with different time-out periods. The multi-function timer consists of an 8-stage divider and a 7-bit prescaler, with the clock source coming from the RTC OSC or the instruction clock (i.e., system clock divided by 4). The multi-function timer also provides a selectable frequency signal (ranging from fS/20 to fS/27) for the VFD driver circuits, and a selectable frequency signal (ranging from fS/21 to fS/28) for the buzzer output by options. It is recommended to select a frequency as close as possible to 32kHz for the VFD driver circuits to obtain good display clarity.
fS D iv id e r ROM C o d e O p tio n
V F D D r iv e r ( fS /2 0 ~ fS /2 7 ) B u z z e r (fS /2 1~ fS /2 8)
Real Time Clock - RTC The real time clock (RTC) is used to supply a regular internal interrupt. Its time-out period ranges from fS/28 to fS/215 by software programming. Writing data to RT2, RT1 and RT0 (bits 2, 1, 0 of RTCC; 09H) yields various time-out periods. If the RTC time-out occurs and the interrupt is enabled, the related interrupt request flag (RTF; bit 1 of MFIS) is set and the multi-function interrupt request flag (MFF; bit 6 of INTC1) is set. If the interrupt (EMFI) is enabled, and the stack is not full, a subroutine call to location 18H occurs. RT2 0 0 0 0 1 1 1 1 RT1 0 0 1 1 0 0 1 1 RT0 0 1 0 1 0 1 0 1 RTC Clock Divided Factor 2 8* 2 9* 210* 211* 212 213 214 215
Note: * not recommended to be used
RTC O SC 32768H z
C o n fig u r a tio n O p tio n
fS C o n fig u r a tio n O p tio n fW fW
DT DT
/2
8
D iv id e r
W DT P r e s c a le r M a s k O p tio n W D T C le a r
CK R
T
CK R
T
W DT 12kH z OSC
T im e - o u t fW D T /2 15~ fW D T /2 14~ fW D T /2 13~ fW D T /2 12~
R eset fW D T /2 1 fW D T /2 1 fW D T /2 1 fW D T /2 1
6 5 4 3
Watchdog Timer
Rev. 1.20
14
April 14, 2006
HT49RV5/HT49CV5
fS D iv id e r RT2 RT1 RT0 P r e s c a le r 8 to 1 M ux. fS /2 8~ fS /2 15 R T C In te rru p t
Real Time Clock The RTCC register descriptions are listed below. Bit No. 0~2 3, 5~7 4 Label RT0~RT2 3/4 QOSC Read/ Write R/W 3/4 R/W Reset 1 3/4 0 Function 8 to 1 multiplexer control inputs to select the real clock prescaler output Unused bit, read as 0 32768Hz OSC quick start-up oscillator 0/1: quick/slow start RTCC (09H) Register Power Down Operation - HALT The HALT mode is initialized by the HALT instruction and results in the following.
* The system oscillator turns off but the WDT oscillator
interrupt is enabled and the stack is not full, the regular interrupt response takes place. If an interrupt request flag is set to 1 before entering the HALT mode, the wake-up function of the related interrupt will be disabled. If a wake-up event occurs, it takes 1024 tSYS (system clock period) to resume normal operation. In other words, a dummy period will be inserted after a wake-up. If the wake-up results from an interrupt acknowledge signal, the actual interrupt subroutine execution will be delayed by one or more cycles. However, if the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished. To minimize power consumption, all the I/O pins should be carefully managed before entering the HALT mode. Reset There are three ways in which a microcontroller reset can occur, through events occurring both internally and externally:
* RES is reset during normal operation * RES is reset during HALT * WDT time-out is reset during normal operation
keeps running (if the WDT oscillator or the real time clock is selected).
* The contents of the on-chip RAM and of the registers
remain unchanged.
* The WDT is cleared and starts recounting (if the WDT
clock source is from the WDT oscillator or the real time clock oscillator).
* All I/O ports maintain their original status. * The PDF flag is set but the TO flag is cleared. * The VFD driver keeps running (if the RTC OSC is se-
lected). The system can leave the HALT mode by means of an external reset, an interrupt, an external falling edge signal on port A, an external rising/falling edge on the RMT pin, or a WDT overflow. An external reset will initialize a chip reset and a WDT overflow will initialize a warm reset. After examining the TO and PDF flags, the source of the reset can be determined. The PDF flag is cleared by a system power-up or by executing the CLR WDT instruction, and is set by executing the HALT instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and SP, the other flags remain in their original status. The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in port A can be independently selected to wake up the device by options. Awakening from an I/O port stimulus, the program will resume execution at the next instruction. If the system is woken up via an interrupt, two possibilities may occur. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. But if the
The WDT time-out reset during HALT is a little different from other kinds of reset. Most of the conditions remain unchanged except that the program counter and stack pointer will be cleared to 0 and the TO flag will be set to 1. Most registers are reset to the initial condition once the reset conditions are met. The different types of resets described affect the reset flags in different ways. These flags, the PDF and TO flags, are located in the status register and are controlled by various microcontroller operations such as the HALT function or Watchdog Timer.
Rev. 1.20
15
April 14, 2006
HT49RV5/HT49CV5
The reset flags are shown in the table: TO 0 u 0 1 1 PDF 0 u 1 u 1 RESET Conditions RES reset during power-up RES reset during normal operation RES Wake-up HALT WDT time-out during normal operation WDT Wake-up HALT Note:
100kW RES 10kW 0 .1 m F *
V
DD
0 .0 1 m F *
Reset Circuit * Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference.
VDD RES S S T T im e - o u t C h ip R eset tS
ST
Note: u stands for unchanged To ensure that the system oscillator is started and stabilized, the SST (System Start-up Timer) provides an extra delay of 1024 system clock pulses when the system awakes from the HALT state or during power-on. An extra SST delay is added during the power-on period, and any wake-up from HALT may enable only the SST delay. The functional unit chip reset status is shown below. Program Counter Interrupt Prescaler, Divider WDT 000H Disabled Cleared Clear. After master reset, WDT begins counting
Reset Timing Chart
HALT W DT W DT T im e - o u t R eset E x te rn a l C o ld R eset
W a rm
R eset
Timer/Event Counter Off Input/Output Ports Stack Pointer Input mode Points to the top of the stack
RES SST 1 0 - b it R ip p le C o u n te r P o w e r - o n D e te c tio n
OSC1
Reset Configuration
The register states are summarized below: Register TMR0H TMR0L TMR0C TMR1H TMR1L TMR1C Program Counter MP0 MP1 BP ACC TBLP TBLH STATUS Reset (Power-on) xxxx xxxx xxxx xxxx 00-0 1000 xxxx xxxx xxxx xxxx 0000 1--0000H xxxx xxxx xxxx xxxx --0- -000 xxxx xxxx xxxx xxxx xxxx xxxx --00 xxxx WDT Time-out RES Reset (Normal Operation) (Normal Operation) uuuu uuuu uuuu uuuu 00-0 1000 uuuu uuuu uuuu uuuu 0000 1--0000H uuuu uuuu uuuu uuuu --0- -000 uuuu uuuu uuuu uuuu uuuu uuuu --1u uuuu uuuu uuuu uuuu uuuu 00-0 1000 uuuu uuuu uuuu uuuu 0000 1--0000H uuuu uuuu uuuu uuuu --0- -000 uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu RES Reset (HALT) uuuu uuuu uuuu uuuu 00-0 1000 uuuu uuuu uuuu uuuu 0000 1--0000H uuuu uuuu uuuu uuuu --0- -000 uuuu uuuu uuuu uuuu uuuu uuuu --01 uuuu WDT Time-out (HALT)* uuuu uuuu uuuu uuuu uu-u uuuu uuuu uuuu uuuu uuuu uuuu u--0000H uuuu uuuu uuuu uuuu --u- -uuu uuuu uuuu uuuu uuuu uuuu uuuu --11 uuuu
Rev. 1.20
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April 14, 2006
HT49RV5/HT49CV5
Register INTC0 INTC1 RMTC MFIS RTCC PA PAC PB PBC PC PCC PD PDC PWM0 PWM1 SBCR SBDR RMT0 RMT1 ADR ADCR ACSR VFDC Note: Reset (Power-on) -000 0000 -000 -000 0000 000---0 0000 ---0 -111 1111 1111 1111 1111 ---- 1111 ---- 1111 11-- ---11-- ---1111 --11 1111 --11 xxxx xxxx xxxx xxxx 0110 0000 xxxx xxxx 0000 0000 0000 0000 xxxx xxxx 01-0 0-00 1--- --00 0000 -111 * stands for warm reset u stands for unchanged x stands for unknown WDT Time-out RES Reset (Normal Operation) (Normal Operation) -000 0000 -000 -000 0000 000---0 0000 ---0 -111 1111 1111 1111 1111 ---- 1111 ---- 1111 11-- ---11-- ---1111 --11 1111 --11 xxxx xxxx xxxx xxxx 0110 0000 xxxx xxxx 0000 0000 0000 0000 xxxx xxxx 01-0 0-00 1--- --00 0000 -111 -000 0000 -000 -000 0000 000---0 0000 ---0 -111 1111 1111 1111 1111 ---- 1111 ---- 1111 11-- ---11-- ---1111 --11 1111 --11 xxxx xxxx xxxx xxxx 0110 0000 xxxx xxxx 0000 0000 0000 0000 xxxx xxxx 01-0 0-00 1--- --00 0000 -111 RES Reset (HALT) -000 0000 -000 -000 0000 000---0 0000 ---0 -111 1111 1111 1111 1111 ---- 1111 ---- 1111 11-- ---11-- ---1111 --11 1111 --11 xxxx xxxx xxxx xxxx 0110 0000 xxxx xxxx 0000 0000 0000 0000 xxxx xxxx 01-0 0-00 ---- --00 0000 -111 WDT Time-out (HALT)* -uuu uuuu -uuu -uuu uuuu uuu---u uuuu ---u -uuu uuuu uuuu uuuu uuuu ---- uuuu ---- uuuu uu-- ---uu-- ---uuuu --uu uuuu --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uu-u u-uu u--- --uu 0000 -111
Timer/Event Counter Two timer/event counters (TMR0,TMR1) are implemented in the microcontroller. The Timer/Event Counter 0 contains a 16-bit programmable count-up counter and the clock may come from an external source or an internal clock source. An internal clock source comes from fSYS. The Timer/Event Counter 1 contains a 16-bit programmable count-up counter and the clock may come from an external source or an internal clock source. An internal clock source comes from fSYS/4 or 32768Hz selected by option. The external clock input allows the user to count external events, measure time intervals or pulse widths, or to generate an accurate time base. There are six registers related to the Timer/Event Counter 0 and Timer/Event Counter 1; TMR0H (0CH), TMR0L (0DH), TMR0C (0EH) and the Timer/Event Counter 1, TMR1H (0FH), TMR1L (10H), and TMR1C (11H). Writing TMR0L (TMR1L) will only place the written data to an internal lower-order byte buffer (8-bit) and writing TMR0H (TMR1H) will transfer the specified data
and the contents of the lower-order byte buffer to TMR0H (TMR1H) and TMR0L (TMR1L) registers, respectively. The Timer/Event Counter 1/0 preload register is changed by each writing TMR0H (TMR1H) operations. Reading TMR0H (TMR1H) will latch the contents of TMR0H (TMR1H) and TMR0L (TMR1L) counters to the destination and the lower-order byte buffer, respectively. Reading the TMR0L (TMR1L) will read the contents of the lower-order byte buffer. The TMR0C (TMR1C) is the Timer/Event Counter 0 (1) control register, which defines the operating mode, counting enable or disable and an active edge. The TM0 and TM1 bits define the operation mode. The event count mode is used to count external events, which means that the clock source is from an external (TMR0, TMR1) pin. The timer mode functions as a normal timer with the clock source coming from the internal selected clock source. Finally, the pulse width measurement mode can be used to count the high or low level duration of the external signal (TMR0, TMR1), and the counting is based on the internal selected clock source. 17 April 14, 2006
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HT49RV5/HT49CV5
In the event count or timer mode, the timer/event counter starts counting at the current contents in the timer/event counter and ends at FFFFH. Once an overflow occurs, the counter is reloaded from the timer/event counter preload register, and generates an interrupt request flag (T0F; bit 6 of INTC0, T1F; bit 4 of INTC1). In the pulse width measurement mode with the values of the TON and TE bits equal to 1, after the TMR0 (TMR1) has received a transient from low to high (or high to low if the TE bit is 0), it will start counting until the TMR0 (TMR1) returns to the original level and resets the TON. Bit No. Label Defines the prescaler stages. T0PSC2, T0PSC1, T0PSC0= 000: fINT=fSYS 001: fINT=fSYS/2 T0PSC0~ 010: fINT=fSYS/4 T0PSC2 011: fINT=fSYS/8 100: fINT=fSYS/16 101: fINT=fSYS/32 110: fINT=fSYS/64 111: fINT=fSYS/128 Defines the TMR0 active edge of the timer/event counter: In Event Counter Mode (T0M1,T0M0)=(0,1): 1:count on falling edge; 0:count on rising edge In Pulse Width measurement mode (T0M1,T0M0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge Enable/disable timer counting (0=disable; 1=enable) Unused bit, read as 0 Defines the operating mode (T0M1, T0M0) 01= Event count mode (External clock) 10= Timer mode (Internal clock) 11= Pulse Width measurement mode (External clock) 00= Unused TMR0C (0EH) Register Bit No. 0~2 Label 3/4 Unused bit, read as 0 Defines the TMR1 active edge of the timer/event counter: In Event Counter Mode (T1M1,T1M0)=(0,1): 1:count on falling edge; 0:count on rising edge In Pulse Width measurement mode (T1M1,T1M0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge Enable/disable timer counting (0= disable; 1= enable) Defines the TMR1 internal clock source (0=fSYS/4; 1=32768Hz) Defines the operating mode (T1M1, T1M0) 01= Event count mode (External clock) 10= Timer mode (Internal clock) 11= Pulse Width measurement mode (External clock) 00= Unused TMR1C (11H) Register Function The measured result remains in the timer/event counter even if the activated transient occurs again. In other words, only 1-cycle measurement can be made until the TON bit is set. The cycle measurement will continue as long as it receives further transient pulse. In this operation mode, the timer/event counter begins counting not according to the logic level but to the transient edges. In the case of counter overflows, the counter is reloaded from the timer/event counter register and issues an interrupt request, as in the other two modes, i.e., the event and timer modes. Function
0~2
3
T0E
4 5
T0ON 3/4 T0M0 T0M1
6 7
3
T1E
4 5
T1ON T1S
6 7
T1M0 T1M1
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April 14, 2006
HT49RV5/HT49CV5
To enable the counting operation, the Timer on bit (TON; bit 4 of TMR0C or TMR1C) should be set to 1. In the pulse width measurement mode, TON is automatically cleared after the measurement cycle is completed. But in the other two modes, TON can only be reset by instructions. The overflow of the Timer/Event Counter 0/1 is one of the wake-up sources and can also be applied to a PFD (Programmable Frequency Divider) output at PA3 by options. Only one PFD (PFD0 or PFD1) can be applied to PA3 by options. No matter what the operation mode is, writing a 0 to ET0I or ET1I disables the related interrupt service. When the PFD function is selected, executing SET [PA].3 instruction will enable the PFD output and executing CLR [PA].3 instruction will disable the PFD output. In the case of timer/event counter OFF condition, writing data to the timer/event counter preload register also reloads that data to the timer/event counter. But if the timer/event counter is turned on, data written to the timer/event counter is kept only in the timer/event counter preload register. The timer/event counter still continues its operation until an overflow occurs.
PW M (6 + 2 ) o r (7 + 1 ) C o m p a re fS
YS
When the timer/event counter (reading TMR0/TMR1) is read, the clock is blocked to avoid errors, as this may results in a counting error. Blocking of the clock should be taken into account by the programmer. It is strongly recommended to load a desired value into the TMR0/TMR1 register first, before turning on the related timer/event counter, for proper operation since the initial value of the TMR0/TMR1 is unknown. Due to the timer/event counter scheme, the programmer should pay special attention on the instruction to enable then disable the timer for the first time, whenever there is a need to use the timer/event counter function, to avoid unpredictable result. After this procedure, the timer/event function can be operated normally. Bits 2~0 of the TMR0C can be used to define the pre-scaling stages of the internal clock sources of the timer/event counter. The definitions are as shown. The overflow signal of the timer/event counter can be used to generate the PFD signal. The timer prescaler is also used as the PWM counter.
T o P D 0 /P D 1
8 - s ta g e P r e s c a le r 8 -1 M U X T0PSC 2~T0PSC 0 TM R0 T0E T0M 1 T0M 0 T0O N P u ls e W id th M e a s u re m e n t M o d e C o n tro l 1 6 - b it T im e r /E v e n t C o u n te r (T M R 0 H /T M R 0 L ) T P A 3 D a ta C T R L O v e r flo w to In te rru p t Q PFD0 f IN
T
D a ta B u s T0M 1 T0M 0 1 6 - b it T im e r /E v e n t C o u n te r P r e lo a d R e g is te r R e lo a d
Timer/Event Counter 0
fS
YS
/4 M
32768H z T1S
U X
f IN
T
D a ta B u s T1M 1 T1M 0 T1E T1M 1 T1M 0 T1O N P u ls e W id th M e a s u re m e n t M o d e C o n tro l 1 6 - b it T im e r /E v e n t C o u n te r (T M R 1 H /T M R 1 L ) T P A 3 D a ta C T R L O v e r flo w to In te rru p t Q PFD1 1 6 - b it T im e r /E v e n t C o u n te r R e lo a d P r e lo a d R e g is te r
TM R1
Timer/Event Counter 1
Rev. 1.20
19
April 14, 2006
HT49RV5/HT49CV5
Remote Control Timer - RMT The HT49RV5/HT49CV5 provides an 8-bit remote control timer that has a pulse width measurement function. Pulse width is measured from a difference in count value when the valid edge (RMT pin) has been detected while the timer operates in the running mode. The RMT pin with rising/falling edge wake-up function, 8-bit timer counter will be cleared during a chip reset. And the RMT clock starts to count after the rising/falling edge trigger.
In te rru p t (R M T 0 F ) N o is e R e je c tio n R is in g E d g e D e te c tio n fS fS
YS YS
RMT M U X fX
L a tc h
R e m o te C o n tr o l T im e r C a p tu r e R e g is te r R M T 0 (2 2 H )
fX /2 5~ fX /2 8 P r e - s c a le r 4 -1 M U X RMS1 RMS0 N o is e R e je c tio n F a llin g E d g e D e te c tio n RME L a tc h R e m o te C o n tr o l T im e r C a p tu r e R e g is te r R M T 1 (2 3 H ) 8 - b it T im e r C o u n te r C le a r
/4
O v e r flo w
(R M T V F )
RMCS
In te rru p t (R M T 1 F )
Remote Control Timer
Bit No. 0 1 2 3 4 5
Label 3/4 ERMT0 ERMT1 ERMTV RME RMCS Unused bit, read as 0
Function
Controls the remote control timer rising edge interrupt (1=enable; 0=disable) Controls the remote control timer falling edge interrupt (1=enable; 0=disable) Controls the remote control timer overflow interrupt (1=enable; 0=disable) Controls the remote control timer (1=enable & start count; 0=disable & clear counter) Selects the remote control timer clock source fX (1=fSYS; 0=fSYS/4) Selects the remote control timer clock 00=fX/25 01= fX/26 10= fX/27 11= fX/28 RMTC (21H) Register
6~7
RMS0 RMS1
Bit No. 0 1 2 3 4 5~7
Label RMTVF RTF RMT0F RMT1F ERTI 3/4
Function Remote control timer overflow interrupt flag (1=indicates that an overflow has occurred; 0=indicates that an overflow has not occurred) Real time clock interrupt flag (1=indicates that an RTC interrupt has occurred; 0=indicates that an RTC interrupt has not occurred) Remote control timer rising edge interrupt flag (1=indicates that a rising edge interrupt has occurred; 0=indicates that a rising edge interrupt has not occurred) Remote control timer falling edge interrupt flag (1=indicates that a falling edge interrupt has occurred; 0=indicates that a falling edge interrupt has not occurred) Controls the real time clock interrupt (1=enable; 0=disable) Unused bit, read as 0 MFIS (29H) Register
Rev. 1.20
20
April 14, 2006
HT49RV5/HT49CV5
Serial Interface The Serial Interface function has four basic signals included. They are the SDI (serial data input), SDO (serial data output), SCK (serial clock) and SCS (slave select pin). Two registers (SBCR & SBDR) unique to the serial interface provide control, status and data storage.
S B E N = 1 , C S E N = 0 ( if p u ll- h ig h e d ) SCS SCK SDI SDO D 7 /D 0 D 7 /D 0 D 6 /D 1 D 6 /D 1 D 5 /D 2 D 5 /D 2 D 4 /D 3 D 4 /D 3 D 3 /D 4 D 3 /D 4 D 2 /D 5 D 2 /D 5 D 1 /D 6 D 1 /D 6 D 0 /D 7 D 0 /D 7 SBEN=CSEN=1
SIO Timing (SIOCLK Configuration is Falling Edge)
S B E N = 1 , C S E N = 0 ( if p u ll- h ig h e d ) SCS SCK SDI SDO D 7 /D 0 D 7 /D 0 D 6 /D 1 D 6 /D 1 D 5 /D 2 D 5 /D 2 D 4 /D 3 D 4 /D 3 D 3 /D 4 D 3 /D 4 D 2 /D 5 D 2 /D 5 D 1 /D 6 D 1 /D 6 D 0 /D 7 D 0 /D 7 SBEN=CSEN=1
SIO Timing (SIOCLK Configuration is Rising Edge) Bit No. 0 1 2 3 4 Label 3/4 WCOL CSEN MLS SBEN Unused bit, read as 0 This bit shows the situation of the buffer SBDR 1: enable (set by SIO) writing to SBDR 0: disable (cleared by user) reading from SBDR Serial bus selection signal Shift first control bit (1: MSB; 0: LSB) Serial bus selection (1: enable; 0: disable) Master/slave mode selection: M1, M0= 00: master mode, baud rate=fSIO 01: master mode, baud rate=fSIO/4 10: master mode, baud rate=fSIO/16 11: slave mode Clock source selection (0: fSYS/4; 1: fRTCOSC) SBCR (1FH) Register
* SBCR: Serial bus control register

Function
5, 6
M0, M1
7
CKS
Bit 4 (SBEN): serial bus enable/disable (1/0)
-
Bit 7 (CKS): clock source selection: fSIO=fSYS/4 or fRTCOSC Bit 6 (M1), Bit 5 (M0): master/slave mode & baud rate selection
-
Enable: (SCS dependent on CSEN bit) Disable (R) enable: SCK, SDI, SDO, SCS=0 and waiting for writing data to SBDR (TXRX buffer) Master mode: write data to SBDR (TXRX buffer) (R) start transmission/reception automatically Master mode: when data has been transferred (R) set TRF Slave mode: when a SCK (and SCS dependent on CSEN) is received, data in TXRX buffer is shifted-out and data on SDI is shifted-in
M1, M0: 00: master mode, baud rate=fSIO 01: master mode, baud rate=fSIO/4 10: master mode, baud rate=fSIO/16 11: slave mode
Rev. 1.20
21
April 14, 2006
HT49RV5/HT49CV5
-
Disable: SCK, SDI, SCS floating, SDO output high
Clock Polarity=Rising Edge or Falling Edge (Configuration Option)
* Serial interface operation

Bit 3 (MLS): MSB or LSB (1/0) shift first control bit Bit 2 (CSEN): serial bus selection signal enable/disable (SCS), when CSEN=0, SCS is floating Bit 1 (WCOL): this bit is set to 1 if data is written to SBDR (TXRX buffer) when data is transferred (R) writing will be ignored if data is written to SBDR (TXRX buffer) when data is transferred Bit 0 (TRF): data transferred or data received (R) used to generate interrupt Note: data receiving is still working when the MCU enters the HALT mode Data written to SBDR (R) write data to TXRX buffer only Data read from SBDR (R) read from SBDR only Operating Mode description
-
Master mode operation Step1: Select CKS and select M1, M0 = 00, 01, 10 Step2: Select CSEN, MLS (the same as the slave) Step3: Set SBEN Step4: Writing data to SBDR
-
data is stored in TXRX buffer output SCK and SCS signals go to step 5 Note: SIO internal operation: * data stored in TXRX buffer, and SDI data is shifted into TXRX buffer * data transferred, data in TXRX buffer is latched into SBDR
* SBDR: Serial bus data register

Step5: Check WCOL
-
WCOL= 1, clear WCOL and go to step 4 WCOL= 0, go to step 6
Master transmitter: clock sending and data I/O started by writing SBDR Master clock sending started by writing SBDR Slave transmitter: data I/O started by clock received Slave receiver: data I/O started by clock received
Step6: Check TRFor waiting for serial bus interrupt Step7: Read data from SBDR Step8: Clear TRF Step9: Go to step 4
D a ta B u s SBDR ( R e c e iv e d D a ta R e g is te r )
D7D6D5D4D3D2D1D0
M U
X
SDO
B u ffe r SBEN
SDO
M LS
M U
In te r n a l B a u d R a te C lo c k EN SCK C lo c k P o la r ity A N D , S ta rt SBEN A N D , S ta rt M U X
X
SDI
C0
C1
C2 AND
TDRF W C O L F la g
M a s te r or S la v e
In te r n a l B u s y F la g W r ite S B D R SBEN W r ite S B D R E n a b le /D is a b le W r ite S B D R SCS M a s te r o r S la v e
A N D , S ta rt EN CSEN SBEN
SIO Block Diagram
Rev. 1.20
22
April 14, 2006
HT49RV5/HT49CV5
Slave mode operation Step1: CKS dont care and select M1, M0 =11 Step2: Select CSEN, MLS (the same as the master) Step3: Set SBEN Step4: Writing data to SBDR
-
data is stored in the TXRX buffer waiting for master clock signal (and SCS): SCK go to step 5 Note: SIO internal operation: * SCK (SCS) received * output data in TXRX buffer and SDI data is shifted into TXRX buffer * data transferred, data in TXRX buffer is latched into SBDR
Some instructions first input data and then follow the output operations. For example, SET [m].i, CLR [m].i, CPL [m], CPLA [m] read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. Each line of port A has the capability of waking-up the device. Each I/O port has a pull-high option. Once the pull-high option is selected, the I/O port has a pull-high resistor, otherwise, theres none. Take note that a non-pull-high I/O port operating in input mode will cause a floating state. The PA3 pin is pin-shared with the PFD signal. If the PFD option is selected, the output signal in the output mode of PA3 will be the PFD signal generated by the timer/event counter overflow signal. The input mode always retains its original functions. Once the PFD option is selected, the PFD output signal is controlled by the PA3 data register only. Writing a 1 to PA3 data register will enable the PFD output function and writing a 0 will force the PA3 pin to remain at 0. The I/O functions of PA3 are shown below. I/O I/P Mode (Normal) PA3 Note: Logical Input O/P (Normal) Logical Output I/P (PFD) Logical Input O/P (PFD) PFD (Timer on)
Step5: Check WCOL
-
WCOL=1, clear WCOL, go to step 4 WCOL=0, go to step 6
Step6: Check TRFor waiting for serial bus interrupt Step7: Read data from SBDR Step8: Clear TRF Step9: Go to step 4 Input/Output Ports There are 20 bidirectional input/output lines in the microcontroller, labeled as PA, PB, PC and PD, which are mapped to the data memory of [12H], [14H], [16H] and [18H], respectively. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction MOV A,[m] (m=12H, 14H, 16H or 18H). For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Each I/O line has its own control register (PAC, PBC, PCC, PDC) to control the input/output configuration. With this control register, CMOS output or Schmitt Trigger input with or without pull-high resistor structures can be reconfigured dynamically under software control. To function as an input, the corresponding latch of the control register must write a 1. The input source also depends on the control register. If the control register bit is 1, the input will read the pad state. If the control register bit is 0, the contents of the latches will move to the in t e rn a l b u s . Th e l at t er i s p o s s i bl e i n t h e read-modify-write instruction. For an output function, CMOS is the only configuration. These control registers are mapped to locations 13H, 15H, 17H and 19H. After a chip reset, these input/output lines remain at high levels or floating state (depending on pull-high options). Each bit of these input/output latches can be set or cleared by SET [m].i and CLR [m].i (m=12H, 14H, 16H or 18H) instructions.
The PFD frequency is the timer/event counter overflow frequency divided by 2.
The descriptions of PFD control signal and PFD output frequency are listed in the following table. Timer PA3 Data PA3 Pad Timer Preload Register State Value OFF OFF ON ON Note: X X N N 0 1 0 1 0 U 0 PFD PFD Frequency X X X fTMR/[2(M-N)]
X stands for unused U stands for unknown M is 65536 for PFD0 or PFD1 N is preload value for timer/event counter fTMR is input clock frequency for timer/event counter
The PA0 and PA1 pins are pin-shared with the BZ and BZ signal, respectively. If the BZ/BZ option is selected, the output signal in the output mode of PA0/PA1 will be the buzzer signal generated by the multi-function timer. The input mode always remains in its original function. Once the BZ/BZ option is selected, the buzzer output signal are controlled by the PA0/PA1 data register only.
Rev. 1.20
23
April 14, 2006
HT49RV5/HT49CV5
V C o n tr o l B it Q D CK S Q P u ll- h ig h
DD
D a ta B u s W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r
D a ta B it Q D CK S Q M U X PFDEN (P A 3 ) U X O P0~O P7
W r ite D a ta R e g is te r
PA PA PA PA PA PB PC PC PD PD PD PD PD PD
2 3 /P 4~P 0 /A 6 7 /R 0 /P 1 /P 4 /IN 5 /IN 6 /T 7 /T
0 /B Z 1 /B Z FD A7 N 0 ~ P B 3 /A N 3 MT WM WM T0 T1 MR MR 1 0 1 0
P A 0 /P A 1 /P A 3 /P D 0 /P D 1 B Z /B Z /P F D /P W M 0 /P W M 1 M R e a d D a ta R e g is te r S y s te m W a k e -u p ( P A o n ly ) IN T IN T TM R TM R 0 fo 1 fo 0 fo 1 fo rP rP rP rP D4 D5 D6 D7 on on on on ly ly ly ly
Input/Output Ports
The I/O function of PA0/PA1 are shown below. PA0 I/O PA1 I/O PA0 Mode PA1 Mode PA0 Data PA1 Data PA0 Pad Status PA1 Pad Status Note: I I I O OOOOOOOO I I I OOOOO
It is recommended that unused or not bonded out I/O lines should be set as output pins by software instructions to avoid consuming power under input floating state. PWM The microcontroller provides a 2 channel and (6+2)/(7+1) (dependent on options) bits PWM output shared with PD0/PD1. The PWM channels have their data registers denoted as PWM0 (1AH), PWM1 (1BH). The frequency source of the PWM counter comes from fSYS. The PWM registers are two 8-bit registers. The waveforms of PWM outputs are as shown. Once the PD0/PD1 are selected as the PWM outputs and the output function of PD0/PD1 are enabled (PDC.0/PDC.1 =0), writing 1 to PD0/PD1 data register will enable the PWM output function and writing 0 will force the PD0/PD1 to remain at 0. A (6+2) bits mode PWM cycle is divided into four modulation cycles (modulation cycle 0~modulation cycle 3). Each modulation cycle has 64 PWM input clock period. In a (6+2) bit PWM function, the contents of the PWM register is divided into two groups. Group 1 of the PWM register is denoted by DC which is the value of PWM.7~PWM.2. The group 2 is denoted by AC which is the value of PWM.1~PWM.0.
XXCBBCBBBB XCXXXCCCBB XXD0 I I I D D0 I I 1 D0 0 B D0 0 1 B 0 0 1 B B X D X X X D1 D D X X I D1 D D 0
I input; O output D, D0, D1 Data B buzzer option, BZ or BZ X dont care C CMOS output
The PB0~PB3 can also be used as A/D converter inputs. The A/D function will be described later. There is a function shared with PD0/PD1. If the PWM function is enabled, the PWM0/PWM1 signal will appear on PD0/PD1 (if PD0/PD1 is operating in the output mode). Writing a 1 to PD0~PD1 data register will enable the PWM output function and writing a 0 will force the PD0~PD1 to remain at 0. The I/O functions of PD0/PD1 are as shown. I/O I/P Mode (Normal) PD0 PD1 Logical Input O/P (Normal) Logical Output I/P (PWM) Logical Input O/P (PWM) PWM0 PWM1
Rev. 1.20
24
April 14, 2006
HT49RV5/HT49CV5
In a (6+2) bits mode PWM cycle, the duty cycle of each modulation cycle is shown in the table. Parameter AC (0~3) iA (7+1) bits mode PWM cycle is divided into two modulation cycles (modulation cycle0~modulation cycle 1). Each modulation cycle has 128 PWM input clock period. In a (7+1) bits PWM function, the contents of the PWM register is divided into two groups. Group 1 of the PWM register is denoted by DC which is the value of PWM.7~PWM.1. The group 2 is denoted by AC which is the value of PWM.0.
The modulation frequency, cycle frequency and cycle duty of the PWM output signal are summarized in the following table. PWM Modulation Frequency PWM Cycle PWM Cycle Frequency Duty [PWM]/256
fSYS/64 for (6+2) bits mode fSYS/256 fSYS/128 for (7+1) bits mode
fS
YS
/2
[P W M ] = 1 0 0 PW M [P W M ] = 1 0 1 PW M [P W M ] = 1 0 2 PW M [P W M ] = 1 0 3 PW M PW M 2 6 /6 4 m o d u la tio n p e r io d : 6 4 /fS M o d u la tio n c y c le 0
YS
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4 M o d u la tio n c y c le 1 PW M
2 6 /6 4 M o d u la tio n c y c le 2 c y c le : 2 5 6 /fS
YS
2 5 /6 4 M o d u la tio n c y c le 3
2 6 /6 4 M o d u la tio n c y c le 0
(6+2) PWM Mode
fS /2
YS
[P W M ] = 1 0 0 PW M [P W M ] = 1 0 1 PW M [P W M ] = 1 0 2 PW M [P W M ] = 1 0 3 PW M 5 2 /1 2 8 PW M m o d u la tio n p e r io d : 1 2 8 /fS M o d u la tio n c y c le 0 PW M c y c le : 2 5 6 /fS
YS YS
5 0 /1 2 8
5 0 /1 2 8
5 0 /1 2 8
5 1 /1 2 8
5 0 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 2 /1 2 8
M o d u la tio n c y c le 1
M o d u la tio n c y c le 0
(7+1) PWM Mode
Rev. 1.20
25
April 14, 2006
HT49RV5/HT49CV5
A/D Converter The 4 channels and 8 bit resolution A/D converter are implemented in these microcontrollers. The reference voltage is VDD. The A/D converter contains 3 special registers which are; ADR (25H), ADCR (26H) and ACSR (27H). The ADR contain the A/D result register is read-only. After the A/D conversion is completed, the ADR should be read to get the conversion result data. The ADCR is an A/D converter control register, which defines the A/D channel number, analog channel select, start A/D conversion control bit and the end of A/D conversion flag. If the user wishes to start an A/D conversion, they should define the PB configuration, select the converted analog channel, and give the START bit a rising edge and falling edge (0(R)1(R)0). At the end of the A/D conversion, the EOCB bit is cleared. The ACSR is the A/D clock setting register, which is used to select the A/D clock source. The A/D converter control register is used to control the A/D converter. Bits 1~0 of the ADCR are used to select an analog input channel. Theres a total of four channels to select. The bit5~bit3 of the ADCR are used to set the PB0~PB3 configurations. PB can be an analog input or digital I/O line determined by these 3 bits. Once a PB line is selected as an analog input, the I/O functions and pull-high resistor of this I/O line are disabled and the A/D Bit No. Label Selects the A/D converter clock source 00= system clock/2 01= system clock/8 10= system clock/32 11= undefined Unused bit, read as 0 For test mode used only ACSR (27H) Register Bit No. 0 1 2, 5 3 4 Label ACS0 ACS1 3/4 PCR0 PCR1 Defines the analog channel select. Unused bit, read as 0 Defines the port B configuration select. If PCR0 and PCR1 are all zero, the ADC circuit is powered off to reduce power consumption Indicates end of A/D conversion. (0= end of A/D conversion) Each time bits 3~4 change state the A/D should be initialised by issuing a START signal, otherwise the EOCB flag may have an undefined condition. See Important note for A/D initialisation. Starts the A/D conversion. 0(R)1(R)0= Start 0(R)1= Reset A/D converter and set EOCB to 1. ADCR (26H) Register Function converter circuit is powered-on. The EOCB bit (bit6 of the ADCR) is the end of A/D conversion flag. Check this bit to know when the A/D conversion is completed. The START bit of the ADCR is used to begin the conversion of the A/D converter. Giving the START bit a rising edge and falling edge means that the A/D conversion has started. In order to ensure that the A/D conversion is completed, the START should remain at 0 until the EOCB is cleared to 0 (end of A/D conversion). Bit 7 of the ACSR is used for testing purposes only. It cannot be used by the user. The bit 1 and bit 0 of the ACSR are used to select the A/D clock sources. When the A/D conversion has completed, the A/D interrupt request flag will be set. The EOCB bit is set to 1 when the START bit is set from 0 to 1. Important Note for A/D initialisation: Special care must be taken to initialise the A/D converter each time the Port B A/D channel selection bits are modified, otherwise the EOCB flag may be in an undefined condition. An A/D initialisation is implemented by setting the START bit high and then clearing it to zero within 10 instruction cycles of the Port B channel selection bits being modified. Note that if the Port B channel selection bits are all cleared to zero then an A/D initialisation is not required. Function
0 1
ADCS0 ADCS1 3/4 TEST
2~6 7
6
EOCB
7
START
Rev. 1.20
26
April 14, 2006
HT49RV5/HT49CV5
ACS1 0 0 1 1 ACS0 0 1 0 1 Analog Input Channel Selection Register ADR Note: Bit7 D7 Bit6 D6 Bit5 D5 Bit4 D4 Bit3 D3 Bit2 D2 Bit1 D1 Bit0 D0 Analog Channel AN0 AN1 AN2 AN3
D0~D7 is the A/D conversion result data bit LSB~MSB.
PCR1 0 0 1 1
PCR0 0 1 0 1
3 PB3 PB3 PB3 AN3
2 PB2 PB2 PB2 AN2
1 PB1 PB1 AN1 AN1
0 PB0 AN0 AN0 AN0
Port B Configuration The following programming example illustrates how to setup and implement an A/D conversion. The method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete. Example: using EOCB Polling Method to detect end of conversion clr EADI ; disable ADC interrupt mov a,00000001B mov ACSR,a ; setup the ACSR register to select fSYS/8 as the A/D clock mov mov a,00110000B ADCR,a : ; setup ADCR register to configure Port PB0~PB3 as A/D inputs ; and select AN0 to be connected to the A/D converter ; As the Port B channel bits have changed the following START ; signal (0-1-0) must be issued within 10 instruction cycles : Start_conversion: clr START set START clr START Polling_EOC: sz EOCB jmp polling_EOC mov a,ADR mov adr_buffer,a : : jmp Start_conversion
; reset A/D ; start A/D ; poll the ADCR register EOCB bit to detect end of A/D conversion ; continue polling ; read conversion result from the ADR register ; save result to user defined memory
; start next A/D conversion
Rev. 1.20
27
April 14, 2006
HT49RV5/HT49CV5
M in im u m START o n e in s tr u c tio n c y c le n e e d e d , M a x im u m te n in s tr u c tio n c y c le s a llo w e d
EOCB PC R1~ PCR0
A /D tA 00B
DCS
s a m p lin g tim e 11B
A /D tA
DCS
s a m p lin g tim e
A /D tA
DCS
s a m p lin g tim e 00B 1 . P B p o rt s e tu p a s I/O s 2 . A /D c o n v e r te r is p o w e r e d o ff to r e d u c e p o w e r c o n s u m p tio n
11B
10B
AC S1~ ACS0 P o w e r-o n R eset
00B
01B S ta rt o f A /D c o n v e r s io n R e s e t A /D c o n v e rte r
00B S ta rt o f A /D c o n v e r s io n R e s e t A /D c o n v e rte r E n d o f A /D c o n v e r s io n
01B S ta rt o f A /D c o n v e r s io n R e s e t A /D c o n v e rte r E n d o f A /D c o n v e r s io n
d o n 't c a r e
1 : D e fin e P B c o n fig u r a tio n 2 : S e le c t a n a lo g c h a n n e l
E n d o f A /D c o n v e r s io n tA D C c o n v e r s io n tim e
tA D C A /D c o n v e r s io n tim e N o te : A /D tA D tA
CS
A /D
tA D C c o n v e r s io n tim e
A /D
DC
c lo c k m u s t b e fS = 3 2 tA D = 7 6 tA D
YS
/2 , fS
YS
/8 o r fS
YS
/3 2
A/D Conversion Timing VFD Display Memory The HT49RV5/HT49CV5 provides an area of embedded data memory for the VFD display. This area is located from 40H to 55H of the RAM at Bank 1. The Bank Pointer (BP; located at 04H of the RAM) is the switch for the RAM and the VFD display memory. When the BP is set as 1, any data written into 40H~55H will affect the VFD display. When the BP is written as 0 any data written into 40H~55H is meant to access the general SEG15~ SEG12 Grid0 Grid1 Grid2 Grid3 Grid4 Grid5 Grid6 Grid7 Grid8 Grid9 Grid10 41HU 43HU 45HU 47HU 49HU 4BHU 4DHU 4FHU 51HU 53HU 55HU SEG11~ SEG8 41HL 43HL 45HL 47HL 49HL 4BHL 4DHL 4FHL 51HL 53HL 55HL SEG7~ SEG4 40HU 42HU 44HU 46HU 48HU 4AHU 4CHU 4EHU 50HU 52HU 54HU SEG3~ SEG0 40HL 42HL 44HL 46HL 48HL 4AHL 4CHL 4EHL 50HL 52HL 54HL VFD Display Memory purpose data memory. The VFD display memory can be read and written to only by an indirect addressing mode using MP1. When data is written into the display data area, it is automatically read by the VFD driver which then generates the corresponding VFD driving signals. To turn the display on or off, a 1 or a 0 is written to the corresponding bit of the display memory, respectively. The figure illustrates the mapping between the display memory and VFD pattern for the HT49RV5/ HT49CV5. b7 HU Higher 4 bits b4 b3 HL Lower 4 bits b0
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HT49RV5/HT49CV5
VFD Display Control Register - VFDC Bit No. Label Function Low Voltage Reset There is a low voltage reset circuit (LVR) implemented in the microcontroller. This function can be enabled/disabled by options. If the supply voltage of the device is within the range 0.9V~VLVR, such as changing a battery, the LVR will automatically reset the device internally. The LVR includes the following specifications:
* The low voltage (0.9V~VLVR) has to remain in its origi-
2~0
Selects the VFD display mode 000= 4 grids, 16 segments 001= 5 grids, 16 segments 010= 6 grids, 16 segments VGS2~ 011= 7 grids, 15 segments VGS0 100= 8 grids, 14 segments 101= 9 grids, 13 segments 110= 10 grids, 12 segments 111= 11 grids, 11 segments 3/4 VFDE Unused bit, read as 0 Controls the VFD display (1=enable; 0=disable)
3 4
nal state for longer than 1ms. If the low voltage state does not exceed 1ms, the LVR will ignore it and will not perform a reset function.
* The LVR uses an OR function with the external RES
7~5
Sets the VFD dimming quantity 000= set pulse width to 1/16. 001= set pulse width to 2/16. 010= set pulse width to 4/16. VDM2~V 011= set pulse width to 10/16. DM0 100= set pulse width to 11/16. 101= set pulse width to 12/16. 110= set pulse width to 13/16. 111= set pulse width to 14/16. VFDC (28H) Register
signal to perform a chip reset. The relationship between VDD and VLVR is shown below.
VDD 5 .5 V V
OPR
5 .5 V
V 3 .0 V 2 .2 V
LVR
At power-on initial, the 11-grid, 11-segment & 1/16 pulse width are set and the VFD display is disabled. VFD clock source may come from the RTC or the system clock/4 (fSYS/4). Note:
G r id 0
VDD 0V VEE VDD 0V VEE VDD 0V VEE VDD 0V VEE VDD 0V VEE
0 .9 V
VOPR is the voltage range for proper chip operation at 4MHz system clock.
G r id 1
G r id 0 S e g m e n ts ON G r id 1 S e g m e n ts ON A ll S e g m e n ts OFF
VFD Driver Output
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HT49RV5/HT49CV5
V 5 .5 V
DD
V
LVR
LVR
D e te c t V o lta g e
0 .9 V 0V R e s e t S ig n a l
R eset *1
N o r m a l O p e r a tio n *2
R eset
Low Voltage Reset Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system clock pulses before starting normal operation. *2: Since the low voltage has to maintain its original state for longer than 1ms, therefore a 1ms delay enters the reset mode. Options The following shows the configuration options in the HT49RV5/HT49CV5. All these options should be defined in order to ensure a properly functioning system. Options OSC type selection. This option is to decide if an RC or crystal or 32768Hz crystal oscillator is chosen as the system clock. fWDT: WDT clock source selection. There are three types of selections: system clock/4 or RTC OSC or WDT OSC fS: VFD, RTC and Buzzer clock source selection. There are two types of selections: system clock/4 or RTC OSC WDT enable/disable selection. WDT can be enabled or disabled by option. WDT time-out period selection. There are four types of selection: WDT clock source divided by fWDT/212~fWDT/213, fWDT/213~fWDT/214, fWDT/214~fWDT/215 or fWDT/215~fWDT/216 CLR WDT times selection. This option defines the method to clear the WDT by instruction. One time means that the CLR WDT instructions can clear the WDT. Two times means only if both of the CLR WDT1 and CLR WDT2 instructions have been executed, the WDT can be cleared. Buzzer output frequency selection. There are eight types of frequency signals for buzzer output: fS/2~fS/28, fS means the clock source selected by options. Wake-up selection. This option defines the wake-up capability. External I/O pins (PA only) all have the capability to wake-up the chip from a HALT by a falling edge. (bit option) Pull-high selection. This option is to determine whether the pull-high resistance is viable or not in the input mode of the I/O ports. PA, PB0~PB3, PC6~PC7, PD0~PD1 and PD4~PD7 can be independently selected. (bit option) RMT Pull-high selection. This option is to determine whether a pull-high resistance is viable or not in the input pin. I/O pins shared with other function selections. PA0/BZ, PA1/BZ, PA3/PFD: PA0, PA1 and PA3 can be set as I/O pins or buzzer outputs. VFD driver clock selection. There are 8 types of frequency signals for the VFD driver circuits: fS/20~fS/27. fS stands for the clock source selection by options. VFD ON/OFF at HALT selection, VFD ON at HALT works only when the VFD clock source selects RTC OSC
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HT49RV5/HT49CV5
Options LVR selection LVR has enable or disable options PFD selection. If PA3 is set as a PFD output, there are two types of selections; One is PFD0 as the PFD output, the other is PFD1 as the PFD output. PFD0, PFD1 are the timer overflow signals of the Timer/Event Counter 0, Timer/Event Counter 1, respectively. PWM selection: (7+1) or (6+2) mode PD0: level output or PWM0 output PD1: level output or PWM1 output INT0 or INT1 triggering edge: Disable; high to low; low to high; low to high or high to low SIOCLK: Serial interface clock. There are falling edge, rising edge or triggering edge CSEN: Serial bus selection: enable or disable WCOL: SBDR write conflict
Application Circuits
V
DD
0 .0 1 m F * 100kW 0 .1 m F
10kW
VDD RES
SEG G SEG ~SE
0 r id 1 G
~SE 0~G 1 /G r 1 5 /G
G1 r id id 1 r id 0
0 5 6
VFD
VEE
VSS SCS CLK SDI SDO
VFD
0 .1 m F
P o w e r S u p p ly
0 .1 m F *
OSC C ir c u it S e e r ig h t s id e 32768H z
OSC1 OSC2
OSC1 R
OSC
fS
YS
/4
R C S y s te m O s c illa to r 5 6 k W < R O S C < 1 .5 M W
OSC2
RMT C1 OSC3 P A 0 /B P A 1 /B PA A 3 /P F A4~PA B 0 /A N B 3 /A N C 6~PC 0 /P W M 1 /P W M D 7 0 3 7 0 1 OSC C ir c u it OSC1 3 2 7 6 8 H z C ry s ta l S y s te m O s c illa to r O S C 1 a n d O S C 2 le ft u n c o n n e c te d P PD PD P P ~ ~ Z Z 2 C2 OSC2 OSC1 C ry s ta l S y s te m O s c illa to r
OSC4 P P D 4 /IN T 0 P D 5 /IN T 1 P D 6 /T M R 0 P D 7 /T M R 1 P
OSC2
H T 4 9 R V 5 /H T 4 9 C V 5
Note:
The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is stable and remains within a valid operating voltage range before bringing RES to high.
Rev. 1.20
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HT49RV5/HT49CV5
Instruction Set Summary
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Add data memory to ACC Add ACC to data memory Add immediate data to ACC Add data memory to ACC with carry Add ACC to data memory with carry Subtract immediate data from ACC Subtract data memory from ACC Subtract data memory from ACC with result in data memory Subtract data memory from ACC with carry Subtract data memory from ACC with carry and result in data memory Decimal adjust ACC for addition with result in data memory 1 1(1) 1 1 1(1) 1 1 1(1) 1 1(1) 1(1) Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV C Description Instruction Cycle Flag Affected
Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC Complement data memory Complement data memory with result in ACC 1 1 1 1(1) 1(1) 1(1) 1 1 1 1(1) 1 Z Z Z Z Z Z Z Z Z Z Z
Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Clear bit of data memory Set bit of data memory 1(1) 1(1) None None Move data memory to ACC Move ACC to data memory Move immediate data to ACC 1 1(1) 1 None None None Rotate data memory right with result in ACC Rotate data memory right Rotate data memory right through carry with result in ACC Rotate data memory right through carry Rotate data memory left with result in ACC Rotate data memory left Rotate data memory left through carry with result in ACC Rotate data memory left through carry 1 1(1) 1 1(1) 1 1(1) 1 1(1) None None C C None None C C Increment data memory with result in ACC Increment data memory Decrement data memory with result in ACC Decrement data memory 1 1(1) 1 1(1) Z Z Z Z
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HT49RV5/HT49CV5
Mnemonic Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: No operation Clear data memory Set data memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of data memory Swap nibbles of data memory with result in ACC Enter power down mode 1 1(1) 1(1) 1 1 1 1(1) 1 1 None None None TO,PDF TO(4),PDF(4) TO(4),PDF(4) None None TO,PDF Read ROM code (current page) to data memory and TBLH Read ROM code (last page) to data memory and TBLH 2(1) 2(1) None None Jump unconditionally Skip if data memory is zero Skip if data memory is zero with data movement to ACC Skip if bit i of data memory is zero Skip if bit i of data memory is not zero Skip if increment data memory is zero Skip if decrement data memory is zero Skip if increment data memory is zero with result in ACC Skip if decrement data memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1(2) 1(2) 1(2) 1(2) 1(3) 1(3) 1(2) 1(2) 2 2 2 2 None None None None None None None None None None None None None Description Instruction Cycle Flag Affected
x: Immediate data m: Data memory address A: Accumulator i: 0~7 number of bits addr: Program memory address O: Flag is affected -: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). : If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). Otherwise the original instruction cycle is unchanged. : and (2) : The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged.
(2)
(3) (1) (4)
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HT49RV5/HT49CV5
Instruction Definition
ADC A,[m] Description Operation Affected flag(s) TO 3/4 ADCM A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,x Description Operation Affected flag(s) TO 3/4 ADDM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Add data memory and carry to the accumulator The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. ACC ACC+[m]+C
Add the accumulator and carry to data memory The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory. [m] ACC+[m]+C
Add data memory to the accumulator The contents of the specified data memory and the accumulator are added. The result is stored in the accumulator. ACC ACC+[m]
Add immediate data to the accumulator The contents of the accumulator and the specified data are added, leaving the result in the accumulator. ACC ACC+x
Add the accumulator to the data memory The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. [m] ACC+[m]
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HT49RV5/HT49CV5
AND A,[m] Description Operation Affected flag(s) TO 3/4 AND A,x Description Operation Affected flag(s) TO 3/4 ANDM A,[m] Description Operation Affected flag(s) TO 3/4 CALL addr Description PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical AND accumulator with data memory Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND [m]
Logical AND immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND x
Logical AND data memory with the accumulator Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory. [m] ACC AND [m]
Subroutine call The instruction unconditionally calls a subroutine located at the indicated address. The program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. The indicated address is then loaded. Program execution continues with the instruction at this address. Stack Program Counter+1 Program Counter addr TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation
Affected flag(s)
CLR [m] Description Operation Affected flag(s)
Clear data memory The contents of the specified data memory are cleared to 0. [m] 00H TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
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HT49RV5/HT49CV5
CLR [m].i Description Operation Affected flag(s) TO 3/4 CLR WDT Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Clear bit of data memory The bit i of the specified data memory is cleared to 0. [m].i 0
Clear Watchdog Timer The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are cleared. WDT 00H PDF and TO 0 TO 0 PDF 0 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
CLR WDT1 Description
Preclear Watchdog Timer Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0* TO 0* PDF 0* OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation
Affected flag(s)
CLR WDT2 Description
Preclear Watchdog Timer Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0* TO 0* PDF 0* OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation
Affected flag(s)
CPL [m] Description Operation Affected flag(s)
Complement data memory Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. [m] [m] TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4
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HT49RV5/HT49CV5
CPLA [m] Description Complement data memory and place result in the accumulator Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged. ACC [m] TO 3/4 DAA [m] Description PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4
Operation Affected flag(s)
Decimal-Adjust accumulator for addition The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored in the data memory and only the carry flag (C) may be affected. If ACC.3~ACC.0 >9 or AC=1 then [m].3~[m].0 (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0 (ACC.3~ACC.0), AC1=0 and If ACC.7~ACC.4+AC1 >9 or C=1 then [m].7~[m].4 ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ACC.7~ACC.4+AC1,C=C TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
DEC [m] Description Operation Affected flag(s)
Decrement data memory Data in the specified data memory is decremented by 1. [m] [m]-1 TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4
DECA [m] Description Operation Affected flag(s)
Decrement data memory and place result in the accumulator Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]-1 TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4
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HT49RV5/HT49CV5
HALT Description Enter power down mode This instruction stops program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PDF) is set and the WDT time-out bit (TO) is cleared. Program Counter Program Counter+1 PDF 1 TO 0 TO 0 INC [m] Description Operation Affected flag(s) TO 3/4 INCA [m] Description Operation Affected flag(s) TO 3/4 JMP addr Description Operation Affected flag(s) TO 3/4 MOV A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Directly jump The program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. Program Counter addr PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 1 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation
Affected flag(s)
Increment data memory Data in the specified data memory is incremented by 1 [m] [m]+1
Increment data memory and place result in the accumulator Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]+1
Move data memory to the accumulator The contents of the specified data memory are copied to the accumulator. ACC [m]
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HT49RV5/HT49CV5
MOV A,x Description Operation Affected flag(s) TO 3/4 MOV [m],A Description Operation Affected flag(s) TO 3/4 NOP Description Operation Affected flag(s) TO 3/4 OR A,[m] Description Operation Affected flag(s) TO 3/4 OR A,x Description Operation Affected flag(s) TO 3/4 ORM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 No operation No operation is performed. Execution continues with the next instruction. Program Counter Program Counter+1 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move immediate data to the accumulator The 8-bit data specified by the code is loaded into the accumulator. ACC x
Move the accumulator to data memory The contents of the accumulator are copied to the specified data memory (one of the data memories). [m] ACC
Logical OR accumulator with data memory Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR [m]
Logical OR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR x
Logical OR data memory with the accumulator Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. [m] ACC OR [m]
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April 14, 2006
HT49RV5/HT49CV5
RET Description Operation Affected flag(s) TO 3/4 RET A,x Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Return from subroutine The program counter is restored from the stack. This is a 2-cycle instruction. Program Counter Stack
Return and place immediate data in the accumulator The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. Program Counter Stack ACC x TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RETI Description Operation
Return from interrupt The program counter is restored from the stack, and interrupts are enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit. Program Counter Stack EMI 1 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RL [m] Description Operation
Rotate data memory left The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RLA [m] Description Operation
Rotate data memory left and place result in the accumulator Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
Rev. 1.20
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April 14, 2006
HT49RV5/HT49CV5
RLC [m] Description Operation Rotate data memory left through carry The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 C C [m].7 TO 3/4 RLCA [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Affected flag(s)
Rotate left through carry and place result in the accumulator Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 C C [m].7 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
RR [m] Description Operation
Rotate data memory right The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RRA [m] Description Operation
Rotate right and place result in the accumulator Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 [m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RRC [m] Description Operation
Rotate data memory right through carry The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 C C [m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Affected flag(s)
Rev. 1.20
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April 14, 2006
HT49RV5/HT49CV5
RRCA [m] Description Rotate right through carry and place result in the accumulator Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged. ACC.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 C C [m].0 TO 3/4 SBC A,[m] Description Operation Affected flag(s) TO 3/4 SBCM A,[m] Description Operation Affected flag(s) TO 3/4 SDZ [m] Description PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator. ACC ACC+[m]+C
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory. [m] ACC+[m]+C
Skip if decrement data memory is 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, [m] ([m]-1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
SDZA [m] Description
Decrement data memory and place result in ACC, skip if 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, ACC ([m]-1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
Rev. 1.20
42
April 14, 2006
HT49RV5/HT49CV5
SET [m] Description Operation Affected flag(s) TO 3/4 SET [m]. i Description Operation Affected flag(s) TO 3/4 SIZ [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Set data memory Each bit of the specified data memory is set to 1. [m] FFH
Set bit of data memory Bit i of the specified data memory is set to 1. [m].i 1
Skip if increment data memory is 0 The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, [m] ([m]+1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
SIZA [m] Description
Increment data memory and place result in ACC, skip if 0 The contents of the specified data memory are incremented by 1. If the result is 0, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, ACC ([m]+1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
SNZ [m].i Description
Skip if bit i of the data memory is not 0 If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i0
Operation Affected flag(s)
TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Rev. 1.20
43
April 14, 2006
HT49RV5/HT49CV5
SUB A,[m] Description Operation Affected flag(s) TO 3/4 SUBM A,[m] Description Operation Affected flag(s) TO 3/4 SUB A,x Description Operation Affected flag(s) TO 3/4 SWAP [m] Description Operation Affected flag(s) TO 3/4 SWAPA [m] Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+[m]+1
Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. [m] ACC+[m]+1
Subtract immediate data from the accumulator The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+x+1
Swap nibbles within the data memory The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged. [m].3~[m].0 [m].7~[m].4
Swap data memory and place result in the accumulator The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged. ACC.3~ACC.0 [m].7~[m].4 ACC.7~ACC.4 [m].3~[m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
Rev. 1.20
44
April 14, 2006
HT49RV5/HT49CV5
SZ [m] Description Skip if data memory is 0 If the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TO 3/4 SZA [m] Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move data memory to ACC, skip if 0 The contents of the specified data memory are copied to the accumulator. If the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TO 3/4 SZ [m].i Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Skip if bit i of the data memory is 0 If bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i=0
Operation Affected flag(s)
TO 3/4 TABRDC [m] Description Operation
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move the ROM code (current page) to TBLH and data memory The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
TABRDL [m] Description Operation
Move the ROM code (last page) to TBLH and data memory The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
Rev. 1.20
45
April 14, 2006
HT49RV5/HT49CV5
XOR A,[m] Description Operation Affected flag(s) TO 3/4 XORM A,[m] Description Operation Affected flag(s) TO 3/4 XOR A,x Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical XOR accumulator with data memory Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator. ACC ACC XOR [m]
Logical XOR data memory with the accumulator Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected. [m] ACC XOR [m]
Logical XOR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected. ACC ACC XOR x
Rev. 1.20
46
April 14, 2006
HT49RV5/HT49CV5
Package Information
56-pin SSOP (300mil) Outline Dimensions
56 A 1 C C'
29 B 28
G H a F
D E
Symbol A B C C D E F G H a
Dimensions in mil Min. 395 291 8 720 89 3/4 4 25 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 25 3/4 3/4 3/4 3/4 Max. 420 299 12 730 99 3/4 10 35 12 8
Rev. 1.20
47
April 14, 2006
HT49RV5/HT49CV5
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 43F, SEG Plaza, Shen Nan Zhong Road, Shenzhen, China 518031 Tel: 0755-8346-5589 Fax: 0755-8346-5590 ISDN: 0755-8346-5591 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 010-6641-0030, 6641-7751, 6641-7752 Fax: 010-6641-0125 Holmate Semiconductor, Inc. (North America Sales Office) 46712 Fremont Blvd., Fremont, CA 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com Copyright O 2006 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.20
48
April 14, 2006

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